1. Field of the Invention
The present invention relates to an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device provided with power-source lines and ground lines dedicated to a plurality of internal logic circuits.
2. Description of the Related Art
In recent years, a semiconductor integrated-circuit device (may be hereafter referred to as a semiconductor device or a device) uses an internal circuit by driving it with a dedicated power source line and ground line for each functional block. Because an operating voltage is lowered, a noise-malfunction margin tends to decrease. For example, when a specific circuit block switches to a state of consuming much power, a drop of a power-source voltage due to the above state propagates to power-source lines of another circuit block to prevent a circuit block to be easily influenced by the voltage drop from malfunctioning. This type of the device has a problem that it easily causes an electrostatic breakdown. This is described below by using an example of providing independent power-source line and ground line dedicated to an internal circuit for two circuit blocks.
FIG. 12 shows a layout image diagram on the device chip of a conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit. FIG. 13 shows a circuit diagram of the conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit. As shown in FIGS. 12 and 13, a conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit uses a semiconductor device 100 in which a circuit block A101 (internal-circuit region A) and a circuit block B102 (internal-circuit region B) have an equal supply potential but they have power-source systems independent from each other and the power-source system of an input/output circuit 103 (input/output circuit region) is independent, and an inverter 20 connected to a circuit block A is constituted so as to receive an output of an inverter 30 connected to the circuit block B102 as an input signal through a signal line (wiring resistor) 25.
In a circuit having the configuration of a pair of output and input for interfacing the above two circuit blocks each other, when an electrostatic surge is applied between a power-source line 21 for the circuit block A101 (region A) and a ground line 32 for the circuit block B102 (region B), the gate (oxide film) of a P-channel MOS (Metal-Oxide Semiconductor which is hereafter referred to as PMOS) transistor 23 constituting the inverter 20 is easily broken down. Because there is not a route for an electrostatic surge to pass from the power-source line 21 for the circuit block A101 to the ground line 32 for the circuit block B102, the electrostatic surge flows through gates of the N-channel MOS (Metal-Oxide Semiconductor which is hereafter referred to as NMOS) 34 of the inverter 30 and the PMOS transistor 23 of the inverter 20. Even if an electrostatic surge is applied between the power-source line 31 for the circuit block B102 and the ground line 22 for the circuit block A101 or between the power-source line 21 for the circuit block A101 and the power-source line 31 for the circuit block B102, the PMOS transistor 23 constituting the inverter 20 or the gate (oxide film) of the NMOS transistor 24 is broken down because there is not a route through which the electrostatic surge passes. To settle this type of problem, an improved protective circuit is used.
FIG. 14 shows a layout image diagram on the device chip of a conventional improved semiconductor-device electrostatic-breakdown-preventive and protective circuit. FIG. 15 shows a circuit diagram of a conventional improved semiconductor-device electrostatic-breakdown-preventive and protective circuit. In the conventional semiconductor-device electrostatic-breakdown-preventive and protective circuit, by setting a protective transistor 10 between a power-source line 11 and a ground line 12 for an input/output circuit 103 set to the circumferential portion of a device chip, setting protective transistors 26 and 28 between the power-source line 11 and ground line 12 for the input/output circuit 103 and a position between the power-source line 21 and ground line 22 for the circuit block A101 respectively, and moreover setting protective transistors 27 and 29 between the power-source line 11 and ground line 12 for the input/output circuit 103 and a position between the power-source line 31 and the ground line 32 for the circuit block B102 respectively, a route for a surge to pass through the protective transistors 28, 10, and 27 is secured even if the surge is applied between the power-source line 21 of the circuit block A101 and the ground line 32 for the circuit block B102 and moreover, a delay is provided so that a gate oxide film of the PMOS transistor 23 is not broken down before the surge completely flows through these three protective transistors and a surge voltage is not applied to a gate film from the signal line (protective resistor) 25. Thus, constituting a protective circuit by passing through two or three protective transistors is superior in that the transistors can be easily arranged.
As shown by the layout image diagram of the device chip in FIG. 14, because the power-source lines (terminals) 21 and 31 and ground lines (terminals) 22 and 32 for internal blocks intersects the power-source line (terminal) 11 and ground line (terminal) 12 for the input/output circuit at the circumferential portion of the chip with a vertical-height difference, it is possible to easily arrange protective transistors in the vicinity of the intersection. By arranging protective transistors on the intersecting portion, it is possible to easily constitute the protective-circuit network shown in FIG. 15 and protect the gate oxide film of a circuit for interfacing internal circuits each other from an electrostatic surge.
However, because the clock frequency of a device rises, the so-called salicide structure for minimizing the parasitic resistance of a transistor is introduced, an input/output-circuit region is divided into a plurality of subregions, and the total number of protective transistors (number of protective transistors passing from start to end points of an electrostatic surge) constituting a protective-circuit network increases. Therefore, the number of cases is increased in which it is impossible to prevent a gate (oxide film) from being broken down by only increasing the resistance value of the signal line (protective resistor) 25.
The present invention provides a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device performing high-speed operations and capable of solving various problems to which the above-described improved protective-circuit network has become unable to respond, such as the problem of lowered the response characteristic of the protective-circuit network due to changes in process configuration and increases in the number of divided input/output-circuit regions, without increasing an area of the protective circuit or changing processes.
A first aspect of the invention provides an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device, the circuit comprising: a first power-source line and a first ground line for supplying bias to a first internal block; a second power-source line and a second ground line for supplying bias to a second internal block; a third power-source line and a third ground line for supplying bias to an input/output circuit portion; at least one of a first protective transistor provided between the first power-source line and the second power-source line and a second protective transistor provided between the first ground line and the second ground line; third protective transistors respectively disposed at at least two of a position between the first power-source line and the third power-source line, a position between the first ground line and the third ground line, a position between the first power-source line and the third ground line, and a position between the first ground line and the third power-source line; fourth protective transistors disposed at at least two of a position between the second power-source line and the third power-source line, a position between the second ground line and the third ground line, a position between the second power-source line and the third ground line, and a position between the second ground line and the third power-source line; and a connection line for transferring an output signal of the first internal block as an input signal of the second internal block, wherein at least one of the first protective transistor and the second protective transistors is disposed in the vicinity of the connection line.
In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the first aspect, it is preferable that a distance in each of the first protective transistor and the second protective transistor from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of the protective transistors with a metallic wiring, to a gate of the protective transistor is shorter than a distance in each of the third and fourth protective transistors from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of the protective transistor with a metallic wiring, to a gate of the protective transistor.
In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the first aspect, it is allowed that at each of the first protective transistor and the second protective transistor, a compound layer of silicon and metal is formed on the entirety of a surface between a contact hole for connecting an impurity diffusion layer serving as a source and a drain with a metallic wiring, and a gate; and at each of the third and fourth protective transistors, a region, where no compound layer of silicon and metal is formed, is provided between a contact hole for connecting an impurity diffusion layer serving as a source and a drain with a metallic wiring, and a gate.
In the electrostatic-breakdown-preventive and protective circuit for a semiconductor-device of the first aspect, it is preferable that the distance in each of the first protective transistor and the second protective transistor from the contact hole for connecting the impurity diffusion layer serving as the source and the drain of the protective transistor with a metallic wiring, to the gate of the protective transistor has a minimum value possible in a fabrication process.
A second aspect of the invention provides an electrostatic-breakdown-preventive and protective circuit for a semiconductor-device, the circuit comprising: a first power-source line and a first ground line for supplying bias to a first internal block; a second power-source line and a second ground line for supplying bias to a second internal block; a third power-source line and a third ground line for supplying bias to an input/output circuit portion; first protective transistors respectively disposed at at least two of a position between the first power-source line and the third power-source line, a position between the first ground line and the third ground line, and a position between the first power-source line and the third ground line, a position between the first ground line and the third power-source line; second protective transistors respectively disposed at at least two of a position between the second power-source line and the third power-source line, a position between the second ground line and the third ground line, a position between the second power-source line and the third ground line, and a position between the second ground line and the third power-source line; a connection line for transferring an output signal of the first internal block as an input signal of the second internal block; and at least one of a first resistor whose one end is connected to the first power-source line and whose other end is connected to the second power-source line and a second resistor whose one end is connected to the first ground line and whose other end is connected to the second ground line, wherein at least one of the first resistor and the second resistor is disposed in the vicinity of the connection line.
As described above, the invention makes it possible to provide a compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations.